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Disambiguation of "Vallero, Alessandro"

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Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview.

, , , , , , , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 39 (8): 1204-1214 (2015)

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Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview., , , , , , , , , and 1 other author(s). Microprocessors and Microsystems - Embedded Hardware Design, 39 (8): 1204-1214 (2015)A Bayesian model for system level reliability estimation., , , , , , , and . ETS, page 1-2. IEEE, (2015)Microarchitecture level reliability comparison of modern GPU designs: First findings., , , and . ISPASS, page 129-130. IEEE Computer Society, (2017)Cross-layer early reliability evaluation: Challenges and promises., , , , , , , , , and 3 other author(s). IOLTS, page 228-233. IEEE, (2014)SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems., , , , , , , , , and 4 other author(s). IEEE Trans. Computers, 68 (5): 765-783 (2019)Bayesian network early reliability evaluation analysis for both permanent and transient faults., , , , , , , and . IOLTS, page 7-12. IEEE, (2015)A novel methodology to increase fault tolerance in autonomous FPGA-based systems., , , , , and . IOLTS, page 87-92. IEEE, (2014)Resistance impact by long connections on electrical behavior of integrated Memristive Biosensors., , , , and . ISCAS, page 385-388. IEEE, (2016)Memristive Biosensors Integration With Microfluidic Platform., , , , , , and . IEEE Trans. on Circuits and Systems, 63-I (12): 2120-2127 (2016)ReDO: Cross-Layer Multi-Objective Design-Exploration Framework for Efficient Soft Error Resilient Systems., , and . IEEE Trans. Computers, 67 (10): 1462-1477 (2018)