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Disambiguation of "Man, Hugo De"

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Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator.

, , and . DAC, page 25-30. ACM Press, (1989)

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Dr. Hugo Vale University of Stuttgart

Mirja Mannigel University of Stuttgart

Florian Mangold University of Stuttgart

Hon. -Prof. Dr. Jochen Mannhart University of Stuttgart

Alexander Mandl University of Stuttgart

 

Other publications of authors with the same name

Space-time chip equalizer receivers for WCDMA forward link with time-multiplexed pilot., , , , , and . VTC Fall, page 1058-1062. IEEE, (2001)Platform Independent Data Transfer and Storage Exploration Illustrated on Parallel Cavity Detection Algorithm., , and . PDPTA, page 1669-1675. CSREA Press, (1999)Flexible hardware acceleration for multimedia oriented microprocessors., , , , and . MICRO, page 171-177. ACM/IEEE Computer Society, (2000)Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling., , , , and . DATE, page 10296-10301. IEEE Computer Society, (2003)Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver., , , , , and . DATE, page 10642-10649. IEEE Computer Society, (2003)On Nanoscale Integration and Gigascale Complexity in the Post.Com World.. DATE, page 12. IEEE Computer Society, (2002)Design Technology Research and Education for Deep-Submicron Systems of the Next Century.. VTS, page 8-15. IEEE Computer Society, (1999)Multi-thread graph: a system model for real-time embedded software synthesis., , , , and . ED&TC, page 476-481. IEEE Computer Society, (1997)The Formal Semantics Definition of a Multi-Rate DSP Specification Language in HOL., , and . TPHOLs, volume A-20 of IFIP Transactions, page 375-394. North-Holland/Elsevier, (1992)DRESC: a retargetable compiler for coarse-grained reconfigurable architectures., , , , and . FPT, page 166-173. IEEE, (2002)