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Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.

, , , , , and . DSD, page 423-432. IEEE Computer Society, (2006)

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Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions., , , , , and . Euro-Par, volume 4128 of Lecture Notes in Computer Science, page 495-505. Springer, (2006)Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart., , , , , and . DSD, page 423-432. IEEE Computer Society, (2006)Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders., , , , , and . IET Computers & Digital Techniques, 1 (2): 113-119 (2007)A Power-Aware Technique for Functional Units in High-Performance Processors., , , , and . DSD, page 456-459. IEEE Computer Society, (2006)Memories in Complutense Campus., , , , , , and . A Tribute to Prof. Dr. Da Ruan, page 143-150. Springer, (2013)A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors., , , , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 514-523. Springer, (2006)Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width., , , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 40-48. Springer, (2005)