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Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.

J. Colmenar, O. Garnica, J. Lanchares, J. Hidalgo, G. Miñana, and S. López. DSD, page 423-432. IEEE Computer Society, (2006)

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Prof. Dr. Oscar Gabriel University of Stuttgart

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Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders.G. Miñana, J. Hidalgo, J. Lanchares, J. Colmenar, O. Garnica, and S. López. IET Computers & Digital Techniques, 1 (2): 113-119 (2007)Optimizing L1 cache for embedded systems through grammatical evolution.J. Álvarez, J. Colmenar, J. Risco-Martín, J. Lanchares, and O. Garnica. Soft Comput., 20 (6): 2451-2465 (2016)Improving SMT performance: an application of genetic algorithms to configure resizable caches.J. Díaz, J. Hidalgo, F. Fernández, O. Garnica, and S. López. GECCO (Companion), page 2029-2034. ACM, (2009)Modelling Asynchronous Systems using Probability Distribution Functions.J. Colmenar, N. Morón, O. Garnica, J. Lanchares, and J. Hidalgo. PDP, page 3-11. IEEE Computer Society, (2008)Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution.J. Colmenar, J. Risco-Martín, D. Atienza, O. Garnica, J. Hidalgo, and J. Lanchares. GECCO, page 1227-1234. ACM, (2010)Adaptive Cache Memories for SMT Processors.S. López, O. Garnica, D. Albonesi, S. Dropsho, J. Lanchares, and J. Hidalgo. DSD, page 331-338. IEEE Computer Society, (2010)Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays.J. Colmenar, O. Garnica, S. López, J. Hidalgo, J. Lanchares, and R. Hermida. PDP, page 112-119. IEEE Computer Society, (2004)Mixed heuristic and mathematical programming using reference points for dynamic data types optimization in multimedia embedded systems.J. Risco-Martín, J. Hidalgo, D. Atienza, J. Lanchares, and O. Garnica. GECCO, page 1601-1608. ACM, (2009)Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.G. Miñana, O. Garnica, J. Hidalgo, J. Lanchares, and J. Colmenar. PATMOS, volume 3728 of Lecture Notes in Computer Science, page 40-48. Springer, (2005)A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors.G. Miñana, J. Hidalgo, O. Garnica, J. Lanchares, J. Colmenar, and S. López. PATMOS, volume 4148 of Lecture Notes in Computer Science, page 514-523. Springer, (2006)

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Disambiguation of "Garnica, Oscar"

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Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.

Please choose a person to relate this publication to

Prof. Dr. Oscar Gabriel University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Garnica, Oscar"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.

Please choose a person to relate this publication to

Prof. Dr. Oscar Gabriel University of Stuttgart

Other publications of authors with the same name

Disambiguation

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Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.