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Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability.

, , , , , and . SoCC, page 261-268. IEEE, (2007)

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A Practical Application of Full-Feature Alternating Phase-Shifting Technology for a Phase-Aware Standard-Cell Design Flow., , , and . DAC, page 93-96. ACM, (2001)Modeling and Validation of Silicon Contour-Based Extraction and Simulation of Non-Uniform Devices., , , and . CICC, page 615-618. IEEE, (2007)APLYSIE : un circuit neuro-mimétique : réalisation et intégration sur tranche. (APLYSIE: a neuro-mimetic integrated circuit. Design and wafer scale integration).. Grenoble Institute of Technology, France, (1989)Addressing Parametric Impact of Systematic Pattern Variations in Digital IC Design., , , , , and . CICC, page 587-590. IEEE, (2007)Standard Cell Printability Grading and Hot Spot Detection., and . ISQED, page 264-269. IEEE Computer Society, (2005)Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability., , , , , and . SoCC, page 261-268. IEEE, (2007)Layout Printability Optimization Using a Silicon Simulation Methodology., and . ISQED, page 159-164. IEEE Computer Society, (2004)Predictive models and CAD methodology for pattern dependent variability., , and . ASP-DAC, page 213-218. IEEE, (2008)DFM: Linking Design and Manufacturing., and . VLSI Design, page 705-708. IEEE Computer Society, (2005)