Author of the publication

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.

, , and . ASP-DAC, page 315-318. IEEE Computer Society, (1999)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Re-using chip level DFT at board level., , , , , , , and . European Test Symposium, page 1. IEEE Computer Society, (2012)A case study: Leverage IEEE 1687 based method to automate modeling, verification, and test access for embedded instruments in a server processor., , , , , , and . ITC, page 1-10. IEEE, (2015)Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm., , , and . ISMVL, page 215-221. IEEE Computer Society, (1998)Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits., , and . ASP-DAC, page 315-318. IEEE Computer Society, (1999)Symbolic methods for testing digital circuits.. University of Freiburg, Freiburg im Breisgau, Germany, (2003)Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model., , , , , and . ITC, page 1-10. IEEE Computer Society, (2008)Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy., , and . DAC, page 339-344. ACM Press, (1995)Adapting an industrial memory BIST solution for testing CAMs., , , , , , , and . ITC-Asia, page 112-117. IEEE, (2017)Silicon Evaluation of Static Alternative Fault Models., , , , , and . VTS, page 265-270. IEEE Computer Society, (2007)Polynomial Formal Verification of Multipliers., , , , and . VTS, page 150-157. IEEE Computer Society, (1997)