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Disambiguation of "Pan, David Z."

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Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs.

, , , , and . ASP-DAC, page 621-626. IEEE, (2011)

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Qi Pan University of Stuttgart

Dr. Marie Davidova University of Stuttgart

Karthik Pandaram University of Stuttgart

Mehdiye Panzehir University of Stuttgart

Jiaxin Pan University of Stuttgart

 

Other publications of authors with the same name

Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (6): 905-917 (2013)Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (2): 185-196 (2010)Skew Management of NBTI Impacted Gated Clock Trees., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (6): 918-927 (2013)Machine learning and pattern matching in physical design., , , and . ASP-DAC, page 286-293. IEEE, (2015)Chemical-mechanical polishing aware application-specific 3D NoC design., , , and . ICCAD, page 207-212. IEEE Computer Society, (2011)Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC., , , , and . ICCAD, page 563-570. IEEE Computer Society, (2011)A high-performance triple patterning layout decomposer with balanced density., , , , , and . ICCAD, page 163-169. IEEE, (2013)Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction., and . ISQED, page 79-84. IEEE Computer Society, (2006)Total power optimization combining placement, sizing and multi-Vt through slack distribution management., , and . ASP-DAC, page 352-357. IEEE, (2008)BOB-router: A new buffering-aware global router with over-the-block routing resources optimization., , and . ASP-DAC, page 513-518. IEEE, (2014)