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A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM.

, , and . IEEE Trans. VLSI Syst., 27 (7): 1697-1710 (2019)

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Chip-level modeling and analysis of electrical masking of soft errors., , , and . VTS, page 1-6. IEEE Computer Society, (2013)Defects and Faults in Quantum Cellular Automata at Nano Scale., , , and . VTS, page 291-296. IEEE Computer Society, (2004)Aging-aware timing analysis considering combined effects of NBTI and PBTI., , and . ISQED, page 53-59. IEEE, (2013)A mapping algorithm for defect-tolerance of reconfigurable nano-architectures.. ICCAD, page 668-672. IEEE Computer Society, (2005)Stress-aware P/G TSV planning in 3D-ICs., , , and . ASP-DAC, page 94-99. IEEE, (2015)High-level aging estimation for FPGA-mapped designs., and . FPL, page 284-291. IEEE, (2012)Towards dark silicon era in FPGAs using complementary hard logic design., , , , and . FPL, page 1-6. IEEE, (2014)Investigation of NBTI and PBTI induced aging in different LUT implementations., , and . FPT, page 1-8. IEEE, (2011)Investigation of aging effects in different implementations and structures of programmable routing resources of FPGAs., , and . FPT, page 215-219. IEEE, (2012)Representative critical-path selection for aging-induced delay monitoring., , , and . ITC, page 1-10. IEEE Computer Society, (2013)