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Disambiguation of "Kim, Bongjin"

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A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer.

, , , , , , , , and . CICC, page 237-240. IEEE, (2008)

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Kim Meliani University of Stuttgart

Joel Kimmich University of Stuttgart

Do Yeon Kim University of Stuttgart

Dr. Wolfgang Kimmerle University of Stuttgart

Dr. -Ing. Kim Riedmüller University of Stuttgart

 

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Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division., and . IEICE Transactions, 96-B (7): 1772-1779 (2013)Dual-rail decoding of low-density parity-check codes., , and . ISCAS, page 477-480. IEEE, (2010)A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals., , , and . CICC, page 1-4. IEEE, (2014)True Random Number Generator circuits based on single- and multi-phase beat frequency detection., , , , and . CICC, page 1-4. IEEE, (2014)Integral transforms, convolution products, and first variations., , and . Int. J. Math. Mathematical Sciences, 2004 (11): 579-598 (2004)A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation., , , , and . ESSCIRC, page 345-348. IEEE, (2019)Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications., , , , and . ICCAD, page 263-270. ACM, (2012)A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer., , , , , , , , and . CICC, page 237-240. IEEE, (2008)Low-Complexity Tree Architecture for Finding the First Two Minima., , , and . IEEE Trans. on Circuits and Systems, 62-II (1): 61-64 (2015)Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes., , , , , , and . IEEE Trans. VLSI Syst., 22 (7): 1648-1652 (2014)