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A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer.

J. Shin, J. Park, B. Kim, J. Ryu, C. Kim, J. Kim, S. Yang, H. Kim, and J. Kim. CICC, page 237-240. IEEE, (2008)

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Ji Eun Shin University of Stuttgart

Abhishekkumar Shingala University of Stuttgart

Other publications of authors with the same name

A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA.J. Shin, I. Seo, J. Kim, S. Yang, C. Kim, J. Park, H. Kim, M. Kwak, and G. Hong. CICC, page 409-412. IEEE, (2006)At-speed logic BIST using a frozen clock testing strategy.J. Shin, X. Yu, E. Rudnick, and M. Abramovici. ITC, page 64-71. IEEE Computer Society, (2001)A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization.S. Choi, H. Son, J. Shin, S. Lee, B. Kim, H. Park, and J. Sim. IEEE Trans. on Circuits and Systems, 63-I (2): 276-287 (2016)A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer.J. Shin, J. Park, B. Kim, J. Ryu, C. Kim, J. Kim, S. Yang, H. Kim, and J. Kim. CICC, page 237-240. IEEE, (2008)Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface.K. Chae, B. Koo, J. Oh, S. Park, J. Shin, and J. Park. ISOCC, page 140-141. IEEE, (2018)New charge pump circuits for high output voltage and large current drivability.I. Chung, and J. Shin. IEICE Electronic Express, 6 (12): 800-805 (2009)An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme.K. Chae, J. Choi, H. Lee, J. Choi, S. Yi, Y. Nam, S. Hwang, J. Lee, W. Lee, K. Seong and 8 other author(s). VLSI Circuits, page 96-. IEEE, (2019)A genetic approach to automatic bias generation for biased random instruction generation.M. Bose, J. Shin, E. Rudnick, T. Dukes, and M. Abadir. CEC, page 442-448. IEEE, (2001)

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Disambiguation of "Shin, Jongshin"

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A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer.

Please choose a person to relate this publication to

Ji Eun Shin University of Stuttgart

Abhishekkumar Shingala University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Shin, Jongshin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer.

Please choose a person to relate this publication to

Ji Eun Shin University of Stuttgart

Abhishekkumar Shingala University of Stuttgart

Other publications of authors with the same name

Disambiguation

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URL
DOI
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A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer.