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RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits., , , , , , , , and . 3DIC, page 1-8. IEEE, (2013)Impact of intermediate BEOL technology on standard cell performances of 3D VLSI., , , , , , , , , and 3 other author(s). ESSDERC, page 218-221. IEEE, (2016)Recent advances in 3D VLSI integration., , , , , , , , , and 7 other author(s). ICICDT, page 1-4. IEEE, (2016)Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells., , , , , , , , , and 2 other author(s). ISVLSI, page 539-544. IEEE Computer Society, (2017)3DIP: An iterative partitioning tool for monolithic 3D IC., , , , and . 3DIC, page 1-5. IEEE, (2016)Opportunities brought by sequential 3D CoolCube™ integration., , , , , , , , , and 11 other author(s). ESSDERC, page 226-229. IEEE, (2016)Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix., , , and . ISQED, page 404-411. IEEE, (2012)High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques., , , , , , and . IEEE Trans. VLSI Syst., 25 (8): 2296-2306 (2017)