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Disambiguation of "Rajaram, Anand"

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Practical Clock Tree Robustness Signoff Metrics.

, , and . ISQED, page 676-679. IEEE Computer Society, (2008)

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Anand Venkatachalam University of Stuttgart

Mahathi Anand University of Stuttgart

Nivethika Rajaram University of Stuttgart

 

Other publications of authors with the same name

MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (12): 1945-1958 (2010)Improved algorithms for link-based non-tree clock networks for skew variability reduction., , and . ISPD, page 55-62. ACM, (2005)Robust chip-level clock tree synthesis for SOC designs., and . DAC, page 720-723. ACM, (2008)Reducing clock skew variability via cross links., , and . DAC, page 18-23. ACM, (2004)MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks., and . ASP-DAC, page 250-257. IEEE, (2008)Analysis and optimization of NBTI induced clock skew in gated clock trees., , , and . DATE, page 296-299. IEEE, (2009)A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure., , , , , , , , , and 26 other author(s). ISSCC, page 262-601. IEEE, (2007)Robust Chip-Level Clock Tree Synthesis., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (6): 877-890 (2011)Practical Clock Tree Robustness Signoff Metrics., , and . ISQED, page 676-679. IEEE Computer Society, (2008)Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction., and . ISQED, page 79-84. IEEE Computer Society, (2006)