PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Chillet, Daniel"

Author of the publication

copydeleteadd this publication to your clipboard
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures.

, , and . IJCNN, page 102-107. IEEE, (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Daniel Marino

Daniel Roth

Daniel Roth

Daniel Roth

Daniel Roth

 

Other publications of authors with the same name

A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals., , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 51-62. Kluwer, (2001)VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters., , , and . ICASSP, page 671-674. IEEE Computer Society, (1997)DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints., , , and . IPDPS, IEEE Computer Society, (2002)Power consumption model for partial and dynamic reconfiguration., , , and . ReConFig, page 1-8. IEEE, (2012)Memory aspects in signal processing and HLS tool: Some results., , , and . EUSIPCO, page 1-4. IEEE, (1996)Asynchronous timing model for high-level synthesis of DSP applications., , and . EUSIPCO, page 1-4. IEEE, (1998)Parallelism Level Impact on Energy Consumption in Reconfigurable Devices., , , and . SIGARCH Computer Architecture News, 39 (4): 104-105 (2011)Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures., , , , and . Int. J. Reconfig. Comp., (2010)Approximate nanophotonic interconnects., , , and . NOCS, page 9:1-9:7. ACM, (2019)A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures., , and . IJCNN, page 102-107. IEEE, (2007)