%0 Conference Paper %1 conf/ijcnn/ChilletPS07 %A Chillet, Daniel %A Pillement, Sébastien %A Sentieys, Olivier %B IJCNN %D 2007 %I IEEE %K dblp %P 102-107 %T A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. %U http://dblp.uni-trier.de/db/conf/ijcnn/ijcnn2007.html#ChilletPS07 %@ 978-1-4244-1380-5

@inproceedings{conf/ijcnn/ChilletPS07, added-at = {2008-04-21T00:00:00.000+0200}, author = {Chillet, Daniel and Pillement, Sébastien and Sentieys, Olivier}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/21a5f5c30cb93522ef302241d37efba7d/dblp}, booktitle = {IJCNN}, crossref = {conf/ijcnn/2007}, ee = {http://dx.doi.org/10.1109/IJCNN.2007.4370938}, interhash = {edf0c1af7d58a09bbb6c5bc230cad1b5}, intrahash = {1a5f5c30cb93522ef302241d37efba7d}, isbn = {978-1-4244-1380-5}, keywords = {dblp}, pages = {102-107}, publisher = {IEEE}, timestamp = {2016-02-02T12:15:12.000+0100}, title = {A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures.}, url = {http://dblp.uni-trier.de/db/conf/ijcnn/ijcnn2007.html#ChilletPS07}, year = 2007 }