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Disambiguation of "Ye, Andy"

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An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures.

, and . FPL, page 1-11. IEEE, (2016)

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Ye Feng University of Stuttgart

Dr. Andy Steinmann University of Stuttgart

Weizhou Ye University of Stuttgart

 

Other publications of authors with the same name

An Empirical Analysis of the Fidelity of VPR Area Models., and . FCCM, page 138. IEEE Computer Society, (2016)VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling., , , , , , , and . TRETS, 4 (4): 32:1-32:23 (2011)Measuring the power efficiency of subthreshold FPGAs for implementing portable biomedical applications., , and . Microprocessors and Microsystems - Embedded Hardware Design, 36 (3): 151-158 (2012)Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area., and . FCCM, page 223-226. IEEE Computer Society, (2015)Synthesizing datapath circuits for FPGAs with emphasis on area minimization., , and . FPT, page 219-226. IEEE, (2002)Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits., and . IEEE Trans. VLSI Syst., 14 (5): 462-473 (2006)Utilizing multi-bit connections to improve the area efficiency of unidirectional routing resources for routing multi-bit signals on FPGAs., , and . Microprocessors and Microsystems - Embedded Hardware Design, 36 (3): 167-175 (2012)VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling., , , , , , and . FPGA, page 133-142. ACM, (2009)A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays., and . FPL, page 83-88. IEEE, (2008)The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays., and . FPL, page 427-430. IEEE, (2008)