%0 Conference Paper %1 conf/fpl/KhanY16 %A Khan, Farheen Fatima %A Ye, Andy %B FPL %D 2016 %E Ienne, Paolo %E Najjar, Walid A. %E Anderson, Jason %E Brisk, Philip %E Stechele, Walter %I IEEE %K dblp %P 1-11 %T An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2016.html#KhanY16 %@ 978-2-8399-1844-2

@inproceedings{conf/fpl/KhanY16, added-at = {2016-10-04T00:00:00.000+0200}, author = {Khan, Farheen Fatima and Ye, Andy}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2ab09f063e8a4de10ced41f6e63d25581/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2016}, editor = {Ienne, Paolo and Najjar, Walid A. and Anderson, Jason and Brisk, Philip and Stechele, Walter}, ee = {http://dx.doi.org/10.1109/FPL.2016.7577325}, interhash = {ed0929cf0fd2d0f926515c687f87a352}, intrahash = {ab09f063e8a4de10ced41f6e63d25581}, isbn = {978-2-8399-1844-2}, keywords = {dblp}, pages = {1-11}, publisher = {IEEE}, timestamp = {2016-10-05T09:34:11.000+0200}, title = {An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2016.html#KhanY16}, year = 2016 }