Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Automated Conversion of SystemC Fixed-Point Data Types for Hardware Synthesis.

A. Braun, J. Freuer, J. Gerlach, and W. Rosenstiel. VLSI-SOC, page 55-. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Univ. -Prof. Dr. -Ing. Wolfgang Nowak University of Stuttgart

Comparison of Four Competing Invasion Percolation Models for Gas Flow in Porous MediaI. Banerjee, A. Guthke, C. Van de Ven, K. Mumford, and W. Nowak. Preprint, (2023)

Univ. -Prof. Dr. -Ing. Wolfgang Rheinheimer University of Stuttgart

Univ. -Prof. Dr. Wolfgang Kühnel University of Stuttgart

apl. Prof. Dr. Wolfgang Hauber University of Stuttgart

apl. Prof. Dr. Wolfgang Bolse University of Stuttgart

Other publications of authors with the same name

Organizing and Planning the ASIC Design Process by Means of a Multi-agent System.J. Blaschke, C. Sebeke, and W. Rosenstiel. ICAART (1), page 459-463. INSTICC Press, (2010)Checking temporal properties under simulation of executable system descriptions.J. Ruf, D. Hoffmann, T. Kropf, and W. Rosenstiel. HLDVT, page 161-166. IEEE Computer Society, (2000)Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.A. Herkersdorf, H. Aliee, M. Engel, M. Glaß, C. Gimmler-Dumont, J. Henkel, V. Kleeberger, M. Kochte, J. Kühn, D. Mueller-Gritschneder and 10 other author(s). Microelectronics Reliability, 54 (6-7): 1066-1074 (2014)Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures.T. Schweizer, T. Oppold, J. de Oliveira Filho, S. Eisenhardt, K. Blocher, and W. Rosenstiel. FPT, page 381-384. IEEE, (2007)Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection.J. Kühn, T. Schweizer, D. Peterson, T. Kuhn, and W. Rosenstiel. FPT, page 462-465. IEEE, (2013)Automatic synthesis of VLSI architectures for arbitrary lifting-based filter banks and transforms.R. Bartholomä, T. Greiner, F. Kesel, and W. Rosenstiel. ICASSP, page 1401-1404. IEEE, (2008)Behavioral Emulation of Synthesized RT-Level Descriptions Using VLIW Architectures.T. Buchholz, G. Haug, U. Kebschull, G. Koch, and W. Rosenstiel. International Workshop on Rapid System Prototyping, page 70-. IEEE Computer Society, (1998)Shape independent VLSI-architecture design approach for 2D morphological operations with non-flat structuring elements.M. Holzer, F. Schumacher, T. Greiner, and W. Rosenstiel. ICECS, page 579-582. IEEE, (2010)Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments.S. Schmitt, and W. Rosenstiel. DATE, page 96-101. IEEE Computer Society, (2004)Error Classification and Yield Prediction of Chips in Semiconductor Industry Applications.L. Ludwig, E. Sapozhnikova, V. Lunin, and W. Rosenstiel. Neural Computing and Applications, 9 (3): 202-210 (2000)