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Disambiguation of "Schweizer, Thomas"

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Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection.

, , , , and . FPT, page 462-465. IEEE, (2013)

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Thomas Schweizer University of Stuttgart

Timo Schweizer University of Stuttgart

Ulrike Schweizer University of Stuttgart

Martin Schweizer University of Stuttgart

Dipl.-Ing. Thomas Kuestner

Scan time reduction in DWI of the pancreas using simultaneous multislice technique with different acceleration factors: how fast can we go?, , , , , , , and . Proceedings of the International Society for Magnetic Resonance in Medicine (ISMRM), Honolulu, Hawaii, USA, (April 2017)
 

Other publications of authors with the same name

Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures., , , , and . ReConFig, page 12-17. IEEE Computer Society, (2009)Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures., , , , and . ReConFig, page 135-140. IEEE Computer Society, (2011)Eine Tcl-basierte Methode zur Fehlerinjektion und Fehlereffektsimulation/-emulation auf Xilinx-FPGAs., , , and . MBMV, page 59-71. Albert-Ludwigs-Universität Freiburg, (2016)CRC - Concepts and Evaluation of Processor-Like Reconfigurable Architectures (CRC - Konzepte und Bewertung prozessorartig rekonfigurierbarer Architekturen)., , , , and . it - Information Technology, 49 (3): 157- (2007)Low Energy Voltage Dithering in Dual VDD Circuits., , , and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 237-246. Springer, (2009)Adaptive multi-layer techniques for increased system dependability, , , , , , , , , and 2 other author(s). it - Information Technology, 57 (3): 149-158 (2015)Runtime-datapath-remapping for fault-tolerant coarse-grained reconfigurable architectures., , , , and . ReCoSoC, page 1-2. IEEE, (2011)Optimizing Partial Reconfiguration of Multi-context Architectures., , , and . ReConFig, page 67-72. IEEE Computer Society, (2008)A Fast and Accurate FPGA-Based Fault Injection System., , , , and . FCCM, page 236. IEEE Computer Society, (2013)A Design Environment for Processor-Like Reconfigurable Hardware., , , and . PARELEC, page 171-176. IEEE Computer Society, (2004)