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Disambiguation of "Peng, Xiaochen"

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Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance.

, , , , and . 3DIC, page 1-5. IEEE, (2021)

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Ke Peng University of Stuttgart

Ruoming Peng University of Stuttgart

 

Other publications of authors with the same name

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 37 (12): 3067-3080 (2018)CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training., , , and . MEMSYS, page 490-496. ACM, (2019)Parallelizing SRAM arrays with customized bit-cell for binary neural networks., , , , , , , , and . DAC, page 21:1-21:6. ACM, (2018)XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks., , , , , and . DATE, page 1423-1428. IEEE, (2018)Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis., , , , , , , and . DAC, page 140. ACM, (2019)X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design., , , and . IEEE Trans. on Circuits and Systems, 65-I (10): 3459-3468 (2018)A Versatile ReRAM-based Accelerator for Convolutional Neural Networks., , , , and . SiPS, page 211-216. IEEE, (2018)MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm Optimizations., , and . ICONS, page 1:1-1:7. ACM, (2019)Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons., , , , , and . ASP-DAC, page 574-579. IEEE, (2018)Inference engine benchmarking across technological platforms from CMOS to RRAM., , , , , , , , and . MEMSYS, page 471-479. ACM, (2019)