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Modeling Crosstalk in Resistive VLSI Interconnections.

, , , , and . VLSI Design, page 470-475. IEEE Computer Society, (1999)

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Crosstalk in VLSI interconnections., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (12): 1817-1824 (1999)Power Distribution Topology Design., and . DAC, page 503-507. ACM Press, (1995)Modeling Crosstalk in Resistive VLSI Interconnections., , , , and . VLSI Design, page 470-475. IEEE Computer Society, (1999)Minimal Delay Interconnect Design Using Alphabetic Trees., and . DAC, page 392-396. ACM Press, (1994)Power Distribution Synthesis for VLSI., and . VLSI Design, 1998 (1): 59-72 (1998)Low-power buffered clock tree design., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 16 (9): 965-975 (1997)Clock skew optimization for ground bounce control., , , and . ICCAD, page 395-399. IEEE Computer Society / ACM, (1996)Power Optimal Buffered Clock Tree Design., and . DAC, page 497-502. ACM Press, (1995)Crosstalk reduction for VLSI., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 16 (3): 290-298 (1997)