%0 Journal Article %1 journals/tcad/VittalM97a %A Vittal, Ashok %A Marek-Sadowska, Malgorzata %D 1997 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 9 %P 965-975 %T Low-power buffered clock tree design. %U http://dblp.uni-trier.de/db/journals/tcad/tcad16.html#VittalM97a %V 16

@article{journals/tcad/VittalM97a, added-at = {2016-03-18T00:00:00.000+0100}, author = {Vittal, Ashok and Marek-Sadowska, Malgorzata}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2be87f6a62b9b97139d2a9d77c0242f9e/dblp}, ee = {http://dx.doi.org/10.1109/43.658565}, interhash = {fb8faeea5495ca50e8042c43b37310ae}, intrahash = {be87f6a62b9b97139d2a9d77c0242f9e}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 9, pages = {965-975}, timestamp = {2016-03-19T10:33:49.000+0100}, title = {Low-power buffered clock tree design.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad16.html#VittalM97a}, volume = 16, year = 1997 }