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Alleviate chip I/O pin constraints for multicore processors through optical interconnects.

Z. Wang, J. Xu, P. Yang, X. Wang, Z. Wang, L. Duong, Z. Wang, H. Li, R. Maeda, X. Wu, Y. Ye, and Q. Hao. ASP-DAC, page 791-796. IEEE, (2015)

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Hanchuan Wu University of Stuttgart

Yongxiang Wu University of Stuttgart

Tim Würtele University of Stuttgart

Amelie Wührl University of Stuttgart

PD Dr. phil. Joachim Wündisch University of Stuttgart

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Discovery and Design of Tricyclic Scaffolds as Protein Kinase CK2 (CK2) Inhibitors through a Combination of Shape-Based Virtual Screening and Structure-Based Molecular Modification.H. Sun, X. Xu, X. Wu, X. Zhang, F. Liu, J. Jia, X. Guo, J. Huang, Z. Jiang, T. Feng and 5 other author(s). Journal of Chemical Information and Modeling, 53 (8): 2093-2102 (2013)A NoC Traffic Suite Based on Real Applications.W. Liu, J. Xu, X. Wu, Y. Ye, X. Wang, W. Zhang, M. Nikdast, and Z. Wang. ISVLSI, page 66-71. IEEE Computer Society, (2011)An Novel Effective Simulation Method of Star Atlas for Star Identification.X. Wu, L. Zhao, Y. Hao, and X. Yan. CSO, page 14-17. IEEE Computer Society, (2012)3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.Y. Ye, J. Xu, B. Huang, X. Wu, W. Zhang, X. Wang, M. Nikdast, Z. Wang, W. Liu, and Z. Wang. IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (4): 584-596 (2013)Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.Z. Wang, J. Xu, X. Wu, Y. Ye, W. Zhang, M. Nikdast, X. Wang, and Z. Wang. IEEE Trans. Computers, 63 (6): 1446-1459 (2014)A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.W. Liu, J. Xu, X. Wang, Y. Wang, W. Zhang, Y. Ye, X. Wu, M. Nikdast, and Z. Wang. ISVLSI, page 260-265. IEEE Computer Society, (2011)A Hierarchical Hybrid Optical-Electronic Network-on-Chip.M. Hung, Y. Ye, X. Wu, W. Zhang, W. Liu, and J. Xu. ISVLSI, page 327-332. IEEE Computer Society, (2010)Dynamic Slot Allocation Multiple Access Protocol for Wireless ATM Networks.X. Wu, S. Wu, H. Sun, and L. Li. ICC (3), page 1560-1565. IEEE, (1997)System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.Y. Ye, J. Xu, X. Wu, W. Zhang, X. Wang, M. Nikdast, Z. Wang, and W. Liu. IEEE Trans. VLSI Syst., 21 (2): 292-305 (2013)System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip.Y. Ye, Z. Wang, P. Yang, J. Xu, X. Wu, X. Wang, M. Nikdast, Z. Wang, and L. Duong. IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (11): 1718-1731 (2014)

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Disambiguation of "Wu, Xiaowen"

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Alleviate chip I/O pin constraints for multicore processors through optical interconnects.

Please choose a person to relate this publication to

Hanchuan Wu University of Stuttgart

Yongxiang Wu University of Stuttgart

Tim Würtele University of Stuttgart

Amelie Wührl University of Stuttgart

PD Dr. phil. Joachim Wündisch University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Wu, Xiaowen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Alleviate chip I/O pin constraints for multicore processors through optical interconnects.

Please choose a person to relate this publication to

Hanchuan Wu University of Stuttgart

Yongxiang Wu University of Stuttgart

Tim Würtele University of Stuttgart

Amelie Wührl University of Stuttgart

PD Dr. phil. Joachim Wündisch University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Alleviate chip I/O pin constraints for multicore processors through optical interconnects.