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Controllability of multi-level states in memristive device models using a transistor as current compliance during SET operation., , , and . IJCNN, page 1-8. IEEE, (2015)Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory., , , and . ISCAS, page 1-5. IEEE, (2019)Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays., , , , and . JETC, 14 (2): 30:1-30:14 (2018)Applicability of Well-Established Memristive Models for Simulations of Resistive Switching Devices., , , and . IEEE Trans. on Circuits and Systems, 61-I (8): 2402-2410 (2014)Thermal effects on the I-V characteristics of filamentary VCM based ReRAM-cells using a nanometer-sized heater., , , , , , , and . NVMTS, page 1-5. IEEE, (2017)Kinetic Monte Carlo modeling of the charge transport in a HfO2-based ReRAM with a rough anode., , , and . NVMTS, page 1-4. IEEE, (2017)Memory Devices: Energy-Space-Time Tradeoffs., , , , , , , and . Proceedings of the IEEE, 98 (12): 2185-2200 (2010)A Complementary Resistive Switch-Based Crossbar Array Adder., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (1): 64-74 (2015)Simulation and comparison of two sequential logic-in-memory approaches using a dynamic electrochemical metallization cell model., , , and . Microelectronics Journal, 45 (11): 1416-1428 (2014)In-memory adder functionality in 1S1R arrays., , , , and . ISCAS, page 1338-1341. IEEE, (2015)