Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An Ultra-low Thermal-budget SiGe-base Bipolar Technology

J. Burghartz, D. Grutzmacher, T. Sedgwick, K. Jenkins, A. Megdanis, J. Cotte, D. Nguyen-Ngoc, and S. Iyer. Digest of technical papers : 1993 Symposium on VLSI Technology : May 17 - 19, 1993, Kyoto, page 59-60. Piscataway, New Jersey, IEEE, (1993)
DOI: 10.1109/VLSIT.1993.760244

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Thirumanikandan Subramanian University of Stuttgart

S. Schumann

S. Seemann

S. Wartzack

Boettinger S

Other publications of authors with the same name

Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications.C. Kothandaraman, X. Chen, D. Moy, D. Lea, S. Rosenblatt, F. Khan, D. Leu, T. Kirihata, D. Ioannou, G. Rosa and 3 other author(s). IRPS, page 2. IEEE, (2015)Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration.A. Kumar, Z. Wan, W. Wilcke, and S. Iyer. JETC, 13 (3): 45:1-45:21 (2017)A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.G. Fredeman, D. Plass, A. Mathews, J. Viraraghavan, K. Reyer, T. Knips, T. Miller, E. Gerhard, D. Kannambadi, C. Paone and 12 other author(s). IEEE J. Solid State Circuits, 51 (1): 230-239 (2016)45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications.S. Iyer, G. Freeman, C. Brodsky, A. Chou, D. Corliss, S. Jain, N. Lustig, V. McGahay, S. Narasimha, J. Norum and 10 other author(s). IBM Journal of Research and Development, 55 (3): 5 (2011)A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS.G. Uhlmann, T. Aipperspach, T. Kirihata, K. Chandrasekharan, Y. Li, C. Paone, B. Reed, N. Robson, J. Safran, D. Schmitt and 1 other author(s). ISSCC, page 406-407. IEEE, (2008)Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM.D. Fainstein, S. Rosenblatt, A. Cestero, N. Robson, T. Kirihata, and S. Iyer. VLSIC, page 146-147. IEEE, (2012)An Ultra-low Thermal-budget SiGe-base Bipolar TechnologyJ. Burghartz, D. Grutzmacher, T. Sedgwick, K. Jenkins, A. Megdanis, J. Cotte, D. Nguyen-Ngoc, and S. Iyer. Digest of technical papers : 1993 Symposium on VLSI Technology : May 17 - 19, 1993, Kyoto, page 59-60. Piscataway, New Jersey, IEEE, (1993)A Case for Packageless Processors.S. Pal, D. Petrisko, A. Bajwa, P. Gupta, S. Iyer, and R. Kumar. HPCA, page 466-479. IEEE Computer Society, (2018)Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems.S. Iyer, S. Jangam, and B. Vaisband. IBM Journal of Research and Development, 63 (6): 5:1-5:16 (2019)Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips.N. Robson, J. Safran, C. Kothandaraman, A. Cestero, X. Chen, R. Rajeevakumar, A. Leslie, D. Moy, T. Kirihata, and S. Iyer. CICC, page 799-804. IEEE, (2007)