PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Gupta, Rajesh K."

Author of the publication

copydeleteadd this publication to your clipboard
New models and methods for programming cyber-physical systems (keynote).

, , and . LCTES, page 1-3. ACM, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Shriya Gupta University of Stuttgart

K. Stahl

K. Gaiser

K. Lindow

Ratnesh Kumar Gupta University of Stuttgart

 

Other publications of authors with the same name

Spatial Memoization: Concurrent Instruction Reuse to Correct Timing Errors in SIMD Architectures., , and . IEEE Trans. on Circuits and Systems, 60-II (12): 847-851 (2013)Integrating Embedded Computing Systems Into High School and Early Undergraduate Education., , , , and . IEEE Trans. Education, 54 (2): 197-202 (2011)Test and fault-tolerance issues in pipelined DSP hardware., and . Digital Signal Processing, 1 (3): 134-144 (1991)Underdesigned and Opportunistic Computing in Presence of Hardware Variability., , , , , , , , , and 2 other author(s). IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (1): 8-23 (2013)Duty-cycling buildings aggressively: The next frontier in HVAC control., , , , and . IPSN, page 246-257. IEEE, (2011)SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations., , , and . VLSI Design, page 461-466. IEEE Computer Society, (2003)Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract)., , and . VLSI Design, page 21-23. IEEE Computer Society, (2002)Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components., , and . DAC, page 225-230. (1992)Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories., , , , , and . MICRO, page 385-395. IEEE Computer Society, (2010)ARGO: Aging-aware GPGPU register file allocation., , , , and . CODES+ISSS, page 30:1-30:9. IEEE, (2013)