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CODES+ISSS 2007 guest editors' introduction., and . Design Autom. for Emb. Sys., 13 (1-2): 51-52 (2009)PTL: PCM Translation Layer., , and . ISVLSI, page 380-385. IEEE Computer Society, (2012)Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements., , , , , , , and . PARCO, volume 15 of Advances in Parallel Computing, page 767-776. IOS Press, (2007)A Conservative Approximation Method for the Verification of Preemptive Scheduling Using Timed Automata., , and . IEEE Real-Time and Embedded Technology and Applications Symposium, page 255-264. IEEE Computer Society, (2009)Incorporating compiler feedback into the design of ASIPs., , and . ED&TC, page 508-515. IEEE Computer Society, (1995)Modeling and analysis of fault-tolerant distributed memories for networks-on-chip., , and . DATE, page 1605-1608. EDA Consortium San Jose, CA, USA / ACM DL, (2013)TRAM: A tool for Temperature and Reliability Aware Memory Design., , , , , , and . DATE, page 340-345. IEEE, (2009)REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs., , , , and . IGCC, page 1-10. IEEE Computer Society, (2013)A hypergraph-based model for port allocation on multiple-register-file VLIW architectures., , and . International Journal of Parallel Programming, 23 (6): 499-513 (1995)Trends in Emerging On-Chip Interconnect Technologies., and . IPSJ Trans. System LSI Design Methodology, (2008)