Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Adaptive History-Based Memory Schedulers for Modern Processors., and . IEEE Micro, 26 (1): 22-29 (2006)Profiling and Optimizing Transactional Memory Applications., , , , , , and . International Journal of Parallel Programming, 40 (1): 25-56 (2012)Circuit design of a dual-versioning L1 data cache for optimistic concurrency., , , , , and . ACM Great Lakes Symposium on VLSI, page 325-330. ACM, (2011)Discovering and understanding performance bottlenecks in transactional applications., , , , , , and . PACT, page 285-294. ACM, (2010)A comprehensive approach to DRAM power management., and . HPCA, page 305-316. IEEE Computer Society, (2008)Resource-bounded multicore emulation using Beefarm., , , , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 36 (8): 620-631 (2012)Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor., , , , , and . ROSS@ICS, page 7:1-7:7. ACM, (2014)An Evaluation of High-Level Mechanistic Core Models., , , , and . TACO, 11 (3): 28:1-28:25 (2014)Undersubscribed threading on clustered cache architectures., , , , , and . HPCA, page 678-689. IEEE Computer Society, (2014)TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System., , , , , , , and . FCCM, page 146-153. IEEE Computer Society, (2011)