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MOST-Based Design and Scaling of Synaptic Interconnections in VLSI Analog Array Processing CNN Chips.

, , , , and . VLSI Signal Processing, 23 (2-3): 239-266 (1999)

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Highly linear 2.5-V CMOS ΣΔ modulator for ADSL+., , , , , , and . IEEE Trans. on Circuits and Systems, 51-I (1): 47-62 (2004)A Programmable Imager for Very High Speed Cellular Signal Processing., , , , and . VLSI Signal Processing, 23 (2-3): 305-318 (1999)Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages., , , and . DATE, page 10168-10175. IEEE Computer Society, (2003)Retargeting of mixed-signal blocks for SoCs., , , and . DATE, page 772-775. IEEE Computer Society, (2001)CMOS design of focal plane programmable array processors., , , , and . ESANN, page 57-62. (2001)New Visual Sensors and Processors., , , , , , , , , and 3 other author(s). Spatial Temporal Patterns for Action-Oriented Perception in Roving Robots, volume 1 of Cognitive Systems Monographs, Springer, (2009)IC-constrained optimization of continuous-time Gm-C filters., , and . I. J. Circuit Theory and Applications, 40 (2): 127-143 (2012)Exploration Of Spatial-Temporal Dynamic Phenomena In A 32*32-Cell Stored Program Two-Layer CNN Universal Machine Chip Prototype., , , , , and . Journal of Circuits, Systems, and Computers, 12 (6): 691-710 (2003)Double-sampling single-loop ΣΔ modulator topologies for broad-band applications., , and . IEEE Trans. on Circuits and Systems, 53-II (4): 314-318 (2006)ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs., , , , , , , and . IEEE Trans. on Circuits and Systems, 51-I (5): 851-863 (2004)