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A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design.

, , , , , , , , , , and . CICC, page 1-4. IEEE, (2013)

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Heterogeneous integration of nano enabling devices for 3D ICs., , , , , , , , , and 7 other author(s). ISLPED, page 249-254. IEEE, (2013)A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS., , , , , , , , , and 3 other author(s). IEEE Trans. on Circuits and Systems, 63-I (10): 1746-1757 (2016)Function-based ESD protection circuit design verification for BGA pad-ring array., , , , , , , , , and . ASICON, page 1-4. IEEE, (2015)Field programmable SONOS ESD protection design., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2012)Scalable behavior modeling for SCR based ESD protection structures for circuit simulation., , , , , , , , , and 3 other author(s). ISCAS, page 2333-2336. IEEE, (2014)Post-Si Programmable ESD Protection Circuit Design: Mechanisms and Analysis., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 48 (5): 1237-1249 (2013)Scalable behavior modeling for 3D field-programmable ESD protection structures., , , , , , , , and . CICC, page 1-4. IEEE, (2013)A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2013)