PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Weerasekera, Roshan"

Author of the publication

copydeleteadd this publication to your clipboard
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime.

, , , and . IEEE Trans. VLSI Syst., 16 (5): 589-593 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Weerasekera, Roshan
add a person with the name Weerasekera, Roshan
 

Other publications of authors with the same name

On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits., , , and . DATE, page 1325-1328. IEEE, (2010)3-D memory organization and performance analysis for multi-processor network-on-chip architecture., , , and . 3DIC, page 1-7. IEEE, (2009)Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses., , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 277-285. Springer, (2005)Excitable London: Street map analysis with Oregonator model., , , , and . CoRR, (2018)Scalability of network-on-chip communication architecture for 3-D meshes., , , , , , and . NOCS, page 114-123. IEEE Computer Society, (2009)Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime., , , and . SLIP, page 113-120. ACM, (2006)Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs., , , and . ICCAD, page 212-219. IEEE Computer Society, (2007)Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits., , , , and . 3DIC, page 1-8. IEEE, (2009)Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning., , , and . ICCAD, page 310-317. IEEE Computer Society, (2011)Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime., , , and . IEEE Trans. VLSI Syst., 16 (5): 589-593 (2008)