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Disambiguation of "Giridhar, Bharan"

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Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores.

, , , , , , , , , , , , , , and . ISSCC, page 190-192. IEEE, (2012)

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Other publications of authors with the same name

Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 48 (1): 104-117 (2013)Integrated 3D-stacked server designs for increasing physical density of key-value stores., , , , , and . ASPLOS, page 485-498. ACM, (2014)Scaling towards kilo-core processors with asymmetric high-radix topologies., , , , , , , and . HPCA, page 496-507. IEEE Computer Society, (2013)A 660pW multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronization., , , , and . ISSCC, page 46-48. IEEE, (2011)A fully integrated successive-approximation switched-capacitor DC-DC converter with 31mV output voltage resolution., , , , and . ISSCC, page 370-371. IEEE, (2013)Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores., , , , , , , , , and 5 other author(s). ISSCC, page 190-192. IEEE, (2012)A Sub-nW Multi-stage Temperature Compensated Timer for Ultra-Low-Power Sensor Nodes., , , , and . J. Solid-State Circuits, 48 (10): 2511-2521 (2013)Centip3De: A 64-Core, 3D Stacked Near-Threshold System., , , , , , , , , and 5 other author(s). IEEE Micro, 33 (2): 8-16 (2013)Centip3De: a many-core prototype exploring 3D integration and near-threshold computing., , , , , , , , , and 5 other author(s). Commun. ACM, 56 (11): 97-104 (2013)Exploring DRAM organizations for energy-efficient and resilient exascale memories., , , , , , , , , and . SC, page 23:1-23:12. ACM, (2013)