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Disambiguation of "Dreslinski, Ronald G."

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Scaling towards kilo-core processors with asymmetric high-radix topologies.

, , , , , , , and . HPCA, page 496-507. IEEE Computer Society, (2013)

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G. Daiß

G. Wagner

Dr. Guido Reina University of Stuttgart

Dipl.-Ing. Benjamin Greiner University of Stuttgart

Joachim Groß

 

Other publications of authors with the same name

Embedded way prediction for last-level caches., , and . ICCD, page 167-174. IEEE Computer Society, (2012)Using Graphics Processing Units in an LTE Base Station., , , , , , , and . Signal Processing Systems, 78 (1): 35-47 (2015)Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-cores., , and . ICSAMOS, page 191-198. IEEE, (2014)Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting., , , , , , , and . HPCA, page 271-282. IEEE Computer Society, (2015)Sirius Implications for Future Warehouse-Scale Computers., , , , , , , , , and 1 other author(s). IEEE Micro, 36 (3): 42-53 (2016)Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant., , , , , , , , , and 3 other author(s). ACM Trans. Comput. Syst., 34 (1): 2:1-2:32 (2016)Low power interconnects for SIMD computers., , , , , , and . DATE, page 600-605. IEEE, (2011)Tetris: A Streaming Accelerator for Physics-Limited 3D Plane-Wave Ultrasound Imaging., , , , , , and . DAC, page 189. ACM, (2019)Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores., , , , , , , , , and 5 other author(s). ISSCC, page 190-192. IEEE, (2012)WarpPool: sharing requests with inter-warp coalescing for throughput processors., , , , , , and . MICRO, page 433-444. ACM, (2015)