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Buffer delay change in the presence of power and ground noise.

, , and . IEEE Trans. VLSI Syst., 11 (3): 461-473 (2003)

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Crosstalk in VLSI interconnections., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (12): 1817-1824 (1999)Aggressor alignment for worst-case coupling noise., and . ISPD, page 48-54. ACM, (2000)Coping with buffer delay change due to power and ground noise., , and . DAC, page 860-865. ACM, (2002)Sizing Power/Ground Meshes for Clocking and Computing Circuit Components., , , and . DATE, page 176-183. IEEE Computer Society, (2002)Closed-Form Crosstalk Noise Metrics for Physical Design Applications., and . DATE, page 812-819. IEEE Computer Society, (2002)Modeling Crosstalk in Resistive VLSI Interconnections., , , , and . VLSI Design, page 470-475. IEEE Computer Society, (1999)Buffer delay change in the presence of power and ground noise., , and . IEEE Trans. VLSI Syst., 11 (3): 461-473 (2003)Aggressor alignment for worst-case crosstalk noise., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 20 (5): 612-621 (2001)Efficient Closed-Form Crosstalk Delay Metrics., and . ISQED, page 431-436. IEEE Computer Society, (2002)Incremental delay change due to crosstalk noise., and . ISPD, page 120-125. ACM, (2002)