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Disambiguation of "Ghosh, Sudip"

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Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design.

, , , , , , , , , and . Microelectronics Reliability, 51 (9-11): 1736-1741 (2011)

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Univ. -Prof. Dr. Robin Ghosh University of Stuttgart

Sudip Pal University of Stuttgart

Tufan Ghosh University of Stuttgart

Gautam Ghosh University of Stuttgart

 

Other publications of authors with the same name

Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach., , , , , , and . CSSP, 37 (12): 5690 (2018)Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA., , , , and . ICIT, page 123-128. IEEE, (2014)Advancements on reliability-aware analog circuit design., , , , , , , , , and . ESSCIRC, page 46-52. IEEE, (2012)Design of a Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGA., , , and . ISED, page 68-72. IEEE Computer Society, (2014)Thermal aging model of InP/InGaAs/InP DHBT., , , , , and . Microelectronics Reliability, 50 (9-11): 1554-1558 (2010)FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time., , , and . J. Real-Time Image Processing, 14 (1): 193-221 (2018)Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design., , , , , , , , , and . Microelectronics Reliability, 51 (9-11): 1736-1741 (2011)A rule-based approach for minimizing power dissipation of digital circuits., , , , and . DDECS, page 237-242. IEEE, (2016)Field Programmable Gate Array and System-on-Chip Based Implementation of Discrete Fast Walsh-Hadamard Transform Domain Image Watermarking Architecture for Real-Time Applications., , , and . J. Low Power Electronics, 11 (3): 375-386 (2015)Hardware Design with Real-Time Implementation for Security of Medical Images and EPMR., , , and . Circuits Syst. Signal Process., 41 (2): 867-891 (2022)