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Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach.

S. Das, S. Ghosh, N. Das, S. Maity, H. Rahaman, R. Maity, and N. Maity. CSSP, 37 (12): 5690 (2018)

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A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs.S. Roy, S. Mandal, C. Giri, and H. Rahaman. VLSI-SoC, page 122-127. IEEE, (2015)Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach.S. Das, S. Ghosh, N. Das, S. Maity, H. Rahaman, R. Maity, and N. Maity. CSSP, 37 (12): 5690 (2018)A Galois field-based logic synthesis with testability.J. Mathew, A. Jabir, A. Singh, H. Rahaman, and D. Pradhan. IET Computers & Digital Techniques, 4 (4): 263-273 (2010)Single error correctable bit parallel multipliers over GF(2m).J. Mathew, A. Jabir, H. Rahaman, and D. Pradhan. IET Computers & Digital Techniques, 3 (3): 281-288 (2009)Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips.S. Roy, C. Giri, and H. Rahaman. IET Computers & Digital Techniques, 9 (5): 268-274 (2015)Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability.H. Rahaman, D. Das, and B. Bhattacharya. J. Electronic Testing, 22 (2): 125-142 (2006)Fault diagnosis in reversible circuits under missing-gate fault model.H. Rahaman, D. Kole, D. Das, and B. Bhattacharya. Computers & Electrical Engineering, 37 (4): 475-485 (2011)Bridging fault detection in cluster based FPGA by using Muller C element.N. Das, P. Roy, and H. Rahaman. Computers & Electrical Engineering, 39 (8): 2469-2482 (2013)Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).H. Rahaman, J. Mathew, D. Pradhan, and A. Jabir. IEEE Trans. Computers, 57 (9): 1289-1294 (2008)Diagnosis of SMGF in ESOP Based Reversible Logic Circuit.B. Mondal, C. Bandyopadhyay, D. Kole, J. Mathew, and H. Rahaman. ISED, page 89-93. IEEE Computer Society, (2014)

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Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach.

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Disambiguation of "Rahaman, Hafizur"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach.

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Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach.