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Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis.

, , , , and . ASYNC, page 240-253. IEEE Computer Society, (1997)

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Synthesis methodology for built-in at-speed testing., , and . ICCAD, page 183-188. IEEE Computer Society, (2005)Exploiting area/delay tradeoffs in high-level synthesis., , , and . DATE, page 1024-1029. IEEE, (2012)Realistic performance-constrained pipelining in high-level synthesis., , , and . DATE, page 1382-1387. IEEE, (2011)Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings., , , and . Formal Methods in System Design, 12 (1): 5-38 (1998)Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis., , , , and . ASYNC, page 240-253. IEEE Computer Society, (1997)Quasi-static Scheduling for Concurrent Architectures., , , , and . Fundam. Inform., 62 (2): 171-196 (2004)Incremental high-level synthesis., , , , , , and . ASP-DAC, page 701-706. IEEE, (2010)A region-based theory for state assignment in speed-independent circuits., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 16 (8): 793-812 (1997)Quasi-Static Scheduling for Concurrent Architectures., , , and . ACSD, page 29-40. IEEE Computer Society, (2003)Checking signal transition graph implementability by symbolic BDD traversal., , , , , and . ED&TC, page 325-332. IEEE Computer Society, (1995)