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Generation of minimal size code for scheduling graphs., , and . DATE, page 668-673. IEEE Computer Society, (2001)Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform., , , and . DATE, page 10662-10667. IEEE Computer Society, (2003)Exploiting area/delay tradeoffs in high-level synthesis., , , and . DATE, page 1024-1029. IEEE, (2012)Realistic performance-constrained pipelining in high-level synthesis., , , and . DATE, page 1382-1387. IEEE, (2011)Testing redundant asynchronous circuits by variable phase splitting., , and . EURO-DAC, page 328-333. IEEE Computer Society, (1994)Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL., and . ASYNC, page 84-92. IEEE Computer Society, (2000)Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis., , , , and . ASYNC, page 240-253. IEEE Computer Society, (1997)A Framework for Modeling, Simulation and Automatic Code Generation of Sensor Network Application., , , , and . SECON, page 515-522. IEEE, (2008)Rapid-Prototyping of Embedded Systems via Reprogrammable Devices., , , , , and . RSP, page 133-139. IEEE Computer Society, (1996)Software Development for High-Performance, Reconfigurable, Embedded Multimedia Systems., , and . IEEE Design & Test of Computers, 22 (1): 28-38 (2005)