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Disambiguation of "Hu, Chenming"

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Improved a priori interconnect predictions and technology extrapolation in the GTX system.

, , , , , , , and . IEEE Trans. VLSI Syst., 11 (1): 3-14 (2003)

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Chenming Jiang University of Stuttgart

Huimin Hu University of Stuttgart

Yang Hu University of Stuttgart

Zhiming Hu University of Stuttgart

Nils Huber University of Stuttgart

 

Other publications of authors with the same name

Scaling CMOS devices through alternative structures.. Science in China Series F: Information Sciences, 44 (1): 1-7 (2001)Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis., , , , and . VLSI Design, page 77-. IEEE Computer Society, (2002)Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology., , , , , , , and . ESSCIRC, page 34-37. IEEE, (2012)A non-iterative physical procedure for RF CMOS compact model extraction using BSIM6., , , , , , , and . CICC, page 1-4. IEEE, (2012)Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion., , , , , , and . ISQED, page 185-190. IEEE Computer Society, (2001)Compact Modeling of Variation in FinFET SRAM Cells., , , and . IEEE Design & Test of Computers, 27 (2): 44-50 (2010)Improved a priori interconnect predictions and technology extrapolation in the GTX system., , , , , , , and . IEEE Trans. VLSI Syst., 11 (1): 3-14 (2003)Berkeley reliability tools-BERT., , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 12 (10): 1524-1534 (1993)A charge sheet capacitance model of short channel MOSFETs for SPICE., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 10 (3): 376-389 (1991)Modeling STI Edge Parasitic Current for Accurate Circuit Simulations., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (8): 1291-1294 (2015)