PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Meyer, Fred J."

Author of the publication

copydeleteadd this publication to your clipboard
Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources.

, , , and . DFT, page 368-376. IEEE Computer Society, (1999)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Matthias Meyer University of Stuttgart

Florian Meyer University of Stuttgart

Jens Meyer University of Stuttgart

J. K\"astner

J. Schwarz

 

Other publications of authors with the same name

Guest editorial., and . Journal of Systems Architecture, 50 (5): 237-238 (2004)A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs., , , and . Asian Test Symposium, page 248-253. IEEE Computer Society, (1997)Modeling Defect Spatial Distribution., and . IEEE Trans. Computers, 38 (4): 538-546 (1989)Maximal diagnosis of interconnects of random access memories., , , and . IEEE Trans. Reliability, 52 (4): 423-434 (2003)Sequential diagnosis of processor array systems., , , and . IEEE Trans. Reliability, 53 (4): 487-498 (2004)Measuring the timing jitter of ATE in the frequency domain., , , , , , , , , and . IEEE Trans. Instrumentation and Measurement, 55 (1): 280-289 (2006)Analysis and measurement of fault coverage in a combined ATE and BIST environment., , and . IEEE Trans. Instrumentation and Measurement, 53 (2): 300-307 (2004)Consensus With Dual Failure Modes., and . IEEE Trans. Parallel Distrib. Syst., 2 (2): 214-222 (1991)Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources., , , and . DFT, page 368-376. IEEE Computer Society, (1999)Design Verification of FPGA Implementations., , , , and . IEEE Design & Test of Computers, 16 (2): 66-73 (1999)