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Disambiguation of "Alpert, Charles J."

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A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment.

, , and . IEEE Trans. on Circuits and Systems, 56-II (7): 580-584 (2009)

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Charles Clark University of Stuttgart

J. K\"astner

J. Schwarz

J. K\"astner

J Walter

 

Other publications of authors with the same name

Buffer insertion for noise and delay optimization., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (11): 1633-1645 (1999)Hypergraph partitioning with fixed vertices VLSI CAD., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 19 (2): 267-272 (2000)Minimum buffered routing with bounded capacitive load for slew rate and reliability control., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 22 (3): 241-253 (2003)RC delay metrics for performance optimization., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 20 (5): 571-582 (2001)A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing., , , and . ISCAS, page 1869-1872. IEEE, (1993)Physical Synthesis with Clock-Network Optimization for Large Systems on Chips., , , , , , and . IEEE Micro, 31 (4): 51-62 (2011)A Fast Hierarchical Quadratic Placement Algorithm., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (4): 678-691 (2006)ICCAD-2013 CAD contest in placement finishing and benchmark suite., , , and . ICCAD, page 268-270. IEEE, (2013)Guest editorial., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 22 (4): 385-386 (2003)Faster minimization of linear wirelength for global placement., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 17 (1): 3-13 (1998)