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Physical Synthesis with Clock-Network Optimization for Large Systems on Chips., , , , , , and . IEEE Micro, 31 (4): 51-62 (2011)A Fast Hierarchical Quadratic Placement Algorithm., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (4): 678-691 (2006)ICCAD-2013 CAD contest in placement finishing and benchmark suite., , , and . ICCAD, page 268-270. IEEE, (2013)RC delay metrics for performance optimization., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 20 (5): 571-582 (2001)Hypergraph partitioning with fixed vertices VLSI CAD., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 19 (2): 267-272 (2000)Minimum buffered routing with bounded capacitive load for slew rate and reliability control., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 22 (3): 241-253 (2003)Buffer insertion for noise and delay optimization., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (11): 1633-1645 (1999)A place and route aware buffered Steiner tree construction., , and . ASP-DAC, page 355-360. IEEE Computer Society, (2004)Placement stability metrics., , , and . ASP-DAC, page 1144-1147. ACM Press, (2005)A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing., , , and . ISCAS, page 1869-1872. IEEE, (1993)