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Minimum buffered routing with bounded capacitive load for slew rate and reliability control.

, , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 22 (3): 241-253 (2003)

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A Schema for Multi-Signature Handling Based on Workflow Model., , , , and . IIH-MSP, page 378-381. IEEE Computer Society, (2009)Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs., and . IEEE Trans. VLSI Syst., 15 (11): 1284-1287 (2007)Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation., and . IEEE Trans. VLSI Syst., 23 (9): 1577-1590 (2015)Statistical Timing Analysis in the Presence of Signal-Integrity Effects., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (10): 1873-1877 (2007)Adaptive Vector Flow for Active Contour Model., , and . CCPR, volume 321 of Communications in Computer and Information Science, page 121-128. Springer, (2012)Analysis and extraction of parametric variation effects on microelectrofluidics-based biochips.. BMAS, page 60-65. IEEE, (2009)Intel LVS logic as a combinational logic paradigm in CNT technology., , , , , and . NANOARCH, page 77-81. IEEE Computer Society, (2010)Power/ground supply voltage variation-aware delay test pattern generation., , , and . VTS, page 1-6. IEEE Computer Society, (2014)Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture.. ASP-DAC, page 853-858. IEEE, (2009)Resilient and adaptive performance logic., , and . JETC, 8 (3): 22:1-22:16 (2012)