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Disambiguation of "Jain, Pulkit"

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A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor.

, , , and . J. Solid-State Circuits, 47 (10): 2517-2526 (2012)

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Ripu Jain University of Stuttgart

Shailja Jain University of Stuttgart

 

Other publications of authors with the same name

An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs., , and . ESSDERC, page 262-265. IEEE, (2012)A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor., , , and . J. Solid-State Circuits, 47 (10): 2517-2526 (2012)A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches., , , and . J. Solid-State Circuits, 46 (6): 1495-1505 (2011)A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique., , , , , , , , , and 11 other author(s). ISSCC, page 214-216. IEEE, (2019)A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM., , and . ISLPED, page 119-120. ACM, (2009)Enhancing beneficial jitter using phase-shifted clock distribution., , , and . ISLPED, page 21-26. ACM, (2008)Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design., , , , , and . IEEE Micro, 34 (6): 74-85 (2014)A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches., , , and . J. Solid-State Circuits, 47 (2): 547-559 (2012)A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V., , , , , , , , , and 7 other author(s). ISSCC, page 212-214. IEEE, (2019)The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications., , , , and . IEEE Trans. VLSI Syst., 23 (2): 280-291 (2015)