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Disambiguation of "Chun, Ki Chul"

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A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches.

, , , and . J. Solid-State Circuits, 46 (6): 1495-1505 (2011)

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Phi-Long Chung University of Stuttgart

Annika Kienzlen University of Stuttgart

Complex Physics with Graph Networks for Industrial Material Flow Simulation, , , , , and . 16th CIRP Conference on Intelligent Computation in Manufacturing Engineering, 118, page 50-55. Elsevier, (2023)

Jonathan Kießling University of Stuttgart

Fabian Kianpour University of Stuttgart

Maximilian Kirchner University of Stuttgart

 

Other publications of authors with the same name

A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme., , and . VLSIC, page 130-131. IEEE, (2012)A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode., , and . IEEE Trans. on Circuits and Systems, 60-I (8): 2030-2038 (2013)A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications., , and . J. Solid-State Circuits, 49 (8): 1861-1871 (2014)Variation aware performance analysis of gain cell embedded DRAMs., , and . ISLPED, page 19-24. ACM, (2010)A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies., , , and . ISSCC, page 506-507. IEEE, (2011)A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power mode., , and . CICC, page 1-4. IEEE, (2012)Logic-compatible embedded DRAM design for memory intensive low power systems., , and . ISCAS, page 277-280. IEEE, (2010)A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches., , , and . J. Solid-State Circuits, 47 (2): 547-559 (2012)A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory., , , , , and . J. Solid-State Circuits, 48 (2): 598-610 (2013)A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor., , , and . J. Solid-State Circuits, 47 (10): 2517-2526 (2012)