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Efficient Verification using Generalized Partial Order Analysis.

, , , and . DATE, page 782-789. IEEE Computer Society, (1998)

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Flow Graph Balancing for Minimizing the Required Memory Bandwidth., , , , and . ISSS, page 127-132. ACM / IEEE Computer Society, (1996)Modeling and optimization of hierarchical synchronous circuits., , and . ED&TC, page 144-149. IEEE Computer Society, (1995)Data flow graphs: system specification with the most unrestricted semantics.. EURO-DAC, page 401-405. EEE Computer Society, (1991)Background memory management for dynamic data structure intensive processing systems., , , , and . ICCAD, page 515-520. IEEE Computer Society / ACM, (1995)Minimizing the required memory bandwidth in VLSI system realizations., , , and . IEEE Trans. VLSI Syst., 7 (4): 433-441 (1999)Standards for System-Level Design: Practical Reality or Solution in Search of a Question?, , , , and . DATE, page 576-583. IEEE Computer Society / ACM, (2000)Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer., , , , , , , , , and . DAC, page 76-81. ACM Press, (1998)Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management., , , , , , , , and . VLSI Signal Processing, 21 (3): 185-194 (1999)Efficient Verification using Generalized Partial Order Analysis., , , and . DATE, page 782-789. IEEE Computer Society, (1998)Multi-thread graph: a system model for real-time embedded software synthesis., , , , and . ED&TC, page 476-481. IEEE Computer Society, (1997)