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The vector fixed point unit of the synergistic processor element of the cell architecture processor.

N. Mäding, J. Leenstra, J. Pille, R. Sautter, S. Büttner, S. Ehrenreich, and W. Haller. DATE Designers' Forum, page 244-248. European Design and Automation Association, Leuven, Belgium, (2006)

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Univ. -Prof. Dr. Jens Anders University of Stuttgart

CMOS Integrated Circuits for the Quantum Information SciencesJ. Anders, M. Babaie, J. Bardin, I. Bashir, G. Billiot, E. Blokhina, S. Bonen, E. Charbon, J. Chiaverini, I. Chuang and 19 other author(s). IEEE transactions on quantum engineering, (2023)

Univ. -Prof. Dr. Jens Brockmeyer University of Stuttgart

Jens Wizl University of Stuttgart

Jens Neubeck University of Stuttgart

Data Mining as an essential Tool for Data Driven Vehicle DevelopmentJ. Wegener, S. Putten, J. Neubeck, and A. Wagner. 23. Internationales Stuttgarter Symposium : Automobil- und Motorentechnik, Springer Vieweg, (2023)

Hon. -Prof. Dr. -Ing. Jens Hesselbach University of Stuttgart

Other publications of authors with the same name

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.B. Flachs, S. Asano, S. Dhong, H. Hofstee, G. Gervais, R. Kim, T. Le, P. Liu, J. Leenstra, J. Liberty and 19 other author(s). IBM Journal of Research and Development, 51 (5): 529-544 (2007)Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability.M. Kessler, G. Kiefer, J. Leenstra, K. Schünemann, T. Schwarz, and H. Wunderlich. ITC, page 461-469. IEEE Computer Society, (2001)Hierarchical test assembly for macro based VLSI design.J. Leenstra, and L. Spaanenburg. ITC, page 520-529. IEEE Computer Society, (1990)BIST Power Reduction Using Scan-Chain Disable in the Cell Processor.C. Zoellin, H. Wunderlich, N. Mäding, and J. Leenstra. ITC, page 1-8. IEEE Computer Society, (2006)Scan chain clustering for test power reduction.M. Elm, H. Wunderlich, M. Imhof, C. Zoellin, J. Leenstra, and N. Mäding. DAC, page 828-833. ACM, (2008)Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process.J. Fenkes, T. Gemmeke, and J. Leenstra. J. Low Power Electronics, 3 (1): 54-59 (2007)POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.D. Wendel, R. Kalla, J. Warnock, R. Cargnoni, S. Chu, J. Clabes, D. Dreps, D. Hrusecky, J. Friedrich, M. Islam and 14 other author(s). J. Solid-State Circuits, 46 (1): 145-161 (2011)Custom circuit design as a driver of microprocessor performance.D. Allen, S. Dhong, H. Hofstee, J. Leenstra, K. Nowka, D. Stasiak, and D. Wendel. IBM Journal of Research and Development, 44 (6): 799-822 (2000)IBM POWER8 processor core microarchitecture.B. Sinharoy, J. Norstrand, R. Eickemeyer, H. Le, J. Leenstra, D. Nguyen, B. Konigsburg, K. Ward, M. Brown, J. Moreira and 10 other author(s). IBM Journal of Research and Development, (2015)Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors.J. Walter, J. Leenstra, G. Döttling, B. Leppla, H. Münster, K. Kark, and B. Wile. DAC, page 89-94. ACM Press, (1997)