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A method for generating structurally aligned grids for semiconductor device simulation.

, , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 24 (10): 1485-1491 (2005)

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Evolution of a CMOS Based Lateral High Voltage Technology Concept., , and . Microelectronics Journal, 37 (3): 243-248 (2006)Hot-carrier reliability in high-voltage lateral double-diffused MOS transistors., , , , , , and . IET Circuits, Devices & Systems, 2 (3): 347-353 (2008)A method for generating structurally aligned grids for semiconductor device simulation., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 24 (10): 1485-1491 (2005)High-voltage lateral trench gate SOI-LDMOSFETs., , and . Microelectronics Journal, 35 (3): 299-304 (2004)Improving SiC lateral DMOSFET reliability under high field stress., , , , and . Microelectronics Reliability, 43 (9-11): 1889-1894 (2003)Analysis of hot carrier effects in a 0.35 µm high voltage n-channel LDMOS transistor., , , and . Microelectronics Reliability, 47 (9-11): 1439-1443 (2007)An analytical approach for physical modeling of hot-carrier induced degradation., , , , , , , , and . Microelectronics Reliability, 51 (9-11): 1525-1529 (2011)Interface traps density-of-states as a vital component for hot-carrier degradation modeling., , , , , , , , , and 4 other author(s). Microelectronics Reliability, 50 (9-11): 1267-1272 (2010)