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A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers.

M. Dreschmann, J. Heisswolf, M. Geiger, M. Haußecker, and J. Becker. SBCCI, page 5:1-5:6. ACM, (2015)

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Tim Janz University of Stuttgart

PD Dr. phil. Frank Janle University of Stuttgart

Benedikt Janny

Isabel Janowsky University of Stuttgart

Hon. -Prof. Dr. Martin Jansen University of Stuttgart

Other publications of authors with the same name

NoC simulation in heterogeneous architectures for PGAS programming model.S. Roloff, A. Weichslgartner, J. Heißwolf, F. Hannig, and J. Teich. M-SCOPES, page 77-85. ACM, (2013)Network Interface with Task Spawning Support for NoC-Based DSM Architectures.A. Zaib, J. Heißwolf, A. Weichslgartner, T. Wild, J. Teich, J. Becker, and A. Herkersdorf. ARCS, volume 9017 of Lecture Notes in Computer Science, page 186-198. Springer, (2015)A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers.M. Dreschmann, J. Heisswolf, M. Geiger, M. Haußecker, and J. Becker. SBCCI, page 5:1-5:6. ACM, (2015)Hardware/software debugging of large scale many-core architectures.S. Friederich, J. Heisswolf, and J. Becker. SBCCI, page 45:1-45:7. ACM, (2014)Hardware prototyping of novel invasive multicore architectures.J. Becker, S. Friederich, J. Heisswolf, R. König, and D. May. ASP-DAC, page 201-206. IEEE, (2012)Providing multiple hard latency and throughput guarantees for packet switching networks on chip.J. Heisswolf, R. König, M. Kupper, and J. Becker. Computers & Electrical Engineering, 39 (8): 2603-2622 (2013)Providing fault tolerance through invasive computing.V. Lari, A. Weichslgartner, A. Tanase, M. Witterauf, F. Khosravi, J. Teich, J. Heißwolf, S. Friederich, and J. Becker. it - Information Technology, 58 (6): 309-328 (2016)Hardware Supported Adaptive Data Collection for Networks on Chip.J. Heisswolf, A. Weichslgartner, A. Zaib, R. König, T. Wild, A. Herkersdorf, J. Teich, and J. Becker. IPDPS Workshops, page 153-162. IEEE, (2013)Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers.J. Heisswolf, S. Bischof, M. Rückauer, and J. Becker. SBCCI, page 1-6. IEEE, (2013)Invasive manycore architectures.J. Henkel, A. Herkersdorf, L. Bauer, T. Wild, M. Hübner, R. Pujari, A. Grudnitsky, J. Heisswolf, A. Zaib, B. Vogel and 2 other author(s). ASP-DAC, page 193-200. IEEE, (2012)

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Disambiguation of "Heisswolf, Jan"

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A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers.

Please choose a person to relate this publication to

Tim Janz University of Stuttgart

PD Dr. phil. Frank Janle University of Stuttgart

Benedikt Janny

Isabel Janowsky University of Stuttgart

Hon. -Prof. Dr. Martin Jansen University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Heisswolf, Jan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers.

Please choose a person to relate this publication to

Tim Janz University of Stuttgart

PD Dr. phil. Frank Janle University of Stuttgart

Benedikt Janny

Isabel Janowsky University of Stuttgart

Hon. -Prof. Dr. Martin Jansen University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
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MSOffice XML

A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers.