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Disambiguation of "Becker, Jürgen"

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Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers.

, , , and . SBCCI, page 1-6. IEEE, (2013)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

apl. Prof. Dr. Jürgen Pleiss University of Stuttgart

Univ. -Prof. Dr. Jürgen Pafel University of Stuttgart

Dr. rer. nat. Jürgen Steinwandel University of Stuttgart

Hon. -Prof. Dr. Jürgen Hammer University of Stuttgart

Hon. -Prof. Dr. Jürgen Blum University of Stuttgart

 

Other publications of authors with the same name

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach., , , , , , , , , and 7 other author(s). DSD, page 114-121. IEEE Computer Society, (2012)Virtualization Support for FPGA-Based Coprocessors Connected via PCI Express to an Intel Multicore Platform., , , , and . IPDPS Workshops, page 305-310. IEEE Computer Society, (2014)Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures., , , , , , , , , and 3 other author(s). ICSAMOS, page 228-235. IEEE, (2012)Architecture design space exploration of run-time scalable issue-width processors., , , and . ICSAMOS, page 77-84. IEEE, (2011)A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors., , and . ICSAMOS, page 157-164. IEEE, (2011)Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications., , , , , and . FPL, page 688-691. IEEE, (2007)A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures., , , and . FPL, page 722-725. IEEE, (2007)Dynamic reconfigurable mixed-signal architecture for safety critical applications., , and . FPL, page 503-506. IEEE, (2009)A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput., , , , , and . FPL, page 535-538. IEEE, (2008)Virtualization of heterogeneous and adaptive multi-core/multi-board systems., , , , , and . DASIP, page 1-2. IEEE, (2012)