PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Chuang, Ching-Te"

Author of the publication

copydeleteadd this publication to your clipboard
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.

, , , , , and . VLSI Design, page 125-130. IEEE Computer Society, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dipl.-Ing. Philipp Tempel

Kinematics and dynamics modeling for real-time simulation of the cable-driven parallel robot IPAnema 3, , and . Proceedings of the 14th IFToMM World Congress, page 117-123. Taipei, IFToMM, (2015)

test

Dr. rer. nat. Attila Teleki University of Stuttgart

Dr. -Ing. Kristina Terheiden University of Stuttgart

Carsten Teucher University of Stuttgart

 

Other publications of authors with the same name

A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line., , , , , , and . Microelectronics Journal, (2016)Self-Repairing SRAM Using On-Chip Detection and Compensation., , , , and . IEEE Trans. VLSI Syst., 18 (1): 75-84 (2010)Modeling and Analysis of Leakage Currents in Double-Gate Technologies., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (10): 2052-2061 (2006)SOI Digital Circuits: Design Issues., and . VLSI Design, page 474-479. IEEE Computer Society, (2000)A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , and 9 other author(s). SoCC, page 197-200. IEEE, (2011)Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes., , , , , , , , , and 5 other author(s). IEEE Trans. Biomed. Circuits and Systems, 11 (5): 1013-1025 (2017)All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction., , , , , , and . VLSI-DAT, page 1-4. IEEE, (2015)On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits., , , and . ISQED, page 815-820. IEEE Computer Society, (2008)Testing strategies for a 9T sub-threshold SRAM., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells., , and . ISLPED, page 242-247. ACM, (2016)